 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| XR-T56L22 ...the analog plus company TM Low Power Repeater/Receiver June 1997-3 FEATURES D Contains All The Active Components For A PCM Repeater Or Long Haul Line Receiver D Low Voltage Operation (5.1V) D Low Power Consumption (8.75mA Max) D 2Mbps Operation Capability D Dual Matched ALBO Ports D Internal Adjustable Phase Shift Circuitry D Extracted Clock Output D Internal Shunt Regulator D Temperature Independent Current Biasing APPLICATIONS D T1 PCM Repeater/Receiver D T148C PCM Repeater/Receiver D European 2.048Mbps PCM Repeater/Receiver D Digital Multiplexers, CSUs, Switching Equipment D ISDN Compatible Equipment: Fax Machines, Computers etc. GENERAL DESCRIPTION The XR-T56L22 is a very low power monolithic repeater/ receiver IC designed for PCM carrier systems operating between 1.544Mbps and 2.37Mbps. The IC provides all the active circuitry required to implement one side of a PCM repeater. The XR-T56L22 features on-chip ORDERING INFORMATION Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C adjustable phase shifting, an extracted clock output and an on-board shunt regulator. The very low power consumption of the device makes it ideal for long haul "tandem" repeater applications. Part No. XR-T56L22AP XR-T56L22AN XR-T56L22AD Package 18 Lead 300 Mil PDIP 18 Lead 300 Mil CDIP 18 Lead 300 Mil Jedec SOIC Rev. 1.02 E1997 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1 XR-T56L22 BLOCK DIAGRAM 2 ALBO1 3 ALBO2 1 ANA GND 5 AMP + I/P 4 AMP - I/P + AMP 6 AMP -O/P 7 AMP +O/P ALBO PEAK DET. 18 ALBO FIL Clock Bias GEN. Clock Comparators 16 LC I/P 17 LC Bias 15 Phase Cont. Data Comparators Clock AMP Clock Driver 11 Clock O/P Voltage Ref. Gen. 13 VREF 14 REG Cont. CLK 12 VCC +5 Data Latches D 8 DIG GND CLK Q Output Drivers 10 Data Volt. Reg. 9 D Q Data + Figure 1. XT-T56L22 Block Diagram Rev. 1.02 2 XR-T56L22 PIN CONFIGURATION ANA GND ALBO1 ALBO2 AMP-I/P AMP +I/P AMP -O/P AMP +O/P DIG GND DATA+ 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 ALBO FIL LC BIAS LC I/P PHASE CONT. REG CONT. VREF VCC CLOCK O/P DATA- ANA GND ALBO1 ALBO2 AMP-I/P AMP +I/P AMP -O/P AMP +O/P DIG GND DATA+ 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 ALBO FIL LC BIAS LC I/P PHASE CONT. REG CONT. VREF VCC CLOCK O/P DATA- 18 Lead PDIP, CDIP (0.300") 18 Lead SOIC (Jedec, 0.300") PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Symbol ANA GND ALBO 1 ALBO 2 AMP - I/P AMP + I/P AMP - O/P AMP + O/P DIG GND DATA+ DATACLOCK O/P VCC Description Ground for Analog Sections of IC and Substrate. ALBO PORT 1 Output. Port impedance varies between 25W and 20kW proportional to input signal level. ALBO PORT 2 Output. Similar to pin 2. Inverting Input of Signal Preamp RIN > 20kW. Non-Inverting Input of Signal Preamp. RIN > 20kW. Inverting Output of Signal Pre-amp. Rout < 200W. DC level typically 3.2V. Non-inverting Output of Signal Pre-amp. Similar to pin 6. Ground for Digital Portion of IC. Positive Data Driver Output (Open Collector). VOL < 0.95V @ lOUT = 32mA. Negative Data Driver Output (Open Collector). VOL < 0.95V @ lOUT = 32mA. Phase Shifted Clock Output (Open Collector). Decouple to GND with 0.1mF if not required. With Rpull-up = 1K, VOL < 1.1V @ IOUT = 4mA. Input Pin of Shunt Regulator and Supply Pin for IC. For voltage feed applications the regulator must be disabled and a 5V + 5% supply connected. For line feed a current of 48-120mA is required. ICC < 8.75mA @ RON, ALBO = 25W typical. Output Voltage of Internal Reference of Shunt Regulator. For parallel operation of regulators should be tied to pin 13 of 2nd T56L22 device. VREF approxi-mately VCC/2. Decouple to GND with 0.1mF. Input Voltage of Shunt Regulator Amp. To inhibit regulator, pin should be tied to ground. For line feed operation decouple to GND with 0.1mF. For parallel operation of regulators tie pin 14 of 2nd T56L22 device. VREG approximately VREF. Phase Shift Adjust Input. A resistor to GND from the pin allows adjustment of phase shift from 905 to approximately 05. RP typical 1.8K to 1K. Vphase typical 340mV. Clock Amplifier Input. Pulsed with current from clock comparator. Connect LC tank between 16, 17 for clock recovery. Ickon = --110mA typical. Clock Amplifier Reference Voltage. VLC = 3.6V typical. Control Pin for ALBO Ports. Voltage developed across a capacitor on this pin defines ALBO on impedance VALBO = 1.5V typical. 13 VREF 14 REG CONT 15 16 17 18 PHASE CONT LC I/P LC BIAS ALBO FIL Rev. 1.02 3 XR-T56L22 ELECTRICAL CHARACTERISTICS Test Conditions: TA = -40C to +85C, VCC = 5.1V 5% unless otherwise specified - refer to test circuit (Figure 6). Parameter General Supply Voltage Supply Current Data Output Leakage Current ALBO Port Off Voltage Amplifier Pin Voltage Amplifier Pin Voltage Amplifier Input Impedance Input Offset Voltage Input Bias Current Input Offset Current Output Offset Voltage Common Mode Rejection Ratio Output Volage Swing Clock Amplifier Input Offset Voltage Input Bias Current AC Gain -3db bandwidth Delay ALBO ALBO Filter Resistance ALBO Impedance Match On Current Drive Current Maximum On Impedance Minimum Off Inpedance 18-1 2, 3 1 18 2, 3-1 2, 3-1 20 1.3 0.4 31 57 10 2.4 1.4 25 KW % mA mA W KW 5 5 Pin 12 12 9, 10 2, 3 4, 5 6, 7 4, 5 4, 5 4, 5 4, 5 6, 7 4, 5, 6, 7 6, 7 17, 16 17, 16 Min. 4.85 Typ. Max. 5.35 Unit V mA mA V V Conditions Pin 12, 13 to VCC1 Vpull-up = 8V VCC = 5.35 V1 7 8.75 100 0.1 2.7 3.2 3.7 40 -10 -1 -50 40 1.9 0.5 40 10 35 6 5 10 5 1 50 KW mV mA mV W dB V mV mA dB MHz ns RS = 10K3 4 RS = 8.2K2 RS = 8.2K2 RS = 8.2K2 RS = 8.2K2 Notes 1 Internal regulator disabled. 2 Source Resistance. 3 R = Wou4d3 43wiw5qnd3 PIN 16 positive with respect to Pin 17 S 4 Pin 16 = Pin 17 = 3.6V 5f test = 1MHz Specifications are subject to change without notice Rev. 1.02 4 XR-T56L22 ELECTRICAL CHARACTERISTICS (CON'T) Parameter Threshold Voltages ALBO Threshold +Ve ALBO Threshold -Ve ALBO Threshold Difference Clock Drive on Current + Ve Clock Drive on Current -Ve Clock Drive Difference Clock Threshold +Ve Clock Threshold -Ve Clock Threshold Difference Data Threshold +Ve Data Threshold -Ve Data Threshold Difference Data Output Stages Output Pulse Rise Time + Ve (Tr) Output Pulse Rise -Time-Ve(Tr) Output Pulse Fall Time+Ve(Tf) Output Pulse Fall Time -Ve (Tf) Output Pulse Width +Ve (Tw) Output Pulse Width -Ve (Tw) Output Pulse Width Difference (dTw) Output Voltage (low) (VOL) Output Voltage Difference (VOL) 9, 10 9, 10 9 10 9 10 9 10 224 224 -12 0.6 -0.15 40 40 40 40 264 264 12 0.95 0.15 nS nS nS nS nS nS nS V V 10%-90%6 10%-90%6 10%-90%6 10%-90%6 at 50% at 50% at 50% 6 6 Pin 7, 6 7, 6 Min. 1.4 1.4 -3 80 80 -3 Typ. Max. 1.6 1.6 3 140 140 3 79 79 3 50 50 3 Unit V V % mA mA % % % % % % % Conditions 1, 2 1, 2 3 4 4 3 5 5 3 3 5 3 7, 6 7, 6 7, 6 7, 6 69 69 -3 41 41 -3 Notes 1 Pk/pk voltage at Pins 6 and 7 of a 1MHz sine wave derived through amplifier and measured differentially. 2 Pk/pk voltage at Pins 6 and 7 adjusted for a current increase of 2mA at pin 1. 3 Calculation only: percentage difference = [higher value/lower value]-1 x 100%. 4 V6 - V7 adjusted to ALBO threshold voltage (Pin 16 = 3.6V) 5 Figure taken as a percentage of ALBO threshold. 6 Using a 130W pull up resistor between 9, 10 and VCC and 15pF capacitance to GND. Specifications are subject to change without notice Rev. 1.02 5 XR-T56L22 ELECTRICAL CHARACTERISTICS (CONT'D) Parameter Clock Output Stage Output Pulse Rise Time (Tr) Output Pulse Fall Time (Tf) Output Pulse Width (Tw) Shunt Regulator Output Voltage Voltage Regulation Over Temp. Load Regulation 12 12 12 4.85 5.1 -0.02 0.027 5.35 V %/C %/mA Pin 13, 14 floating Pin 13, 14 floating 1mA to 100mA load 11 11 11 224 40 40 264 ns ns ns 1 Pin Min. Typ. Max. Unit Conditions Note 1 Using a 2K pull up resistor between 11 and VCC and 15pF capacitance to GND. ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . . -65C to 150C Operating Temperature . . . . . . . . . . . . . -40C to 85C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V Supply Voltage Surge (10ms) . . . . . . . . . . . . . . . . . 25V Data Output Voltage (pin 9, 10) . . . . . . . . . . . . . . . 12V SYSTEM DESCRIPTION With reference to the functional block diagram, the basic operation of the XR-T56L22 may be described as follows: The received bipolar signal, is applied to a linear amplifier and automatic equalizer. These circuits provide the necessary amount of gain and phase equalization to recover the transmitted data, and band limit the signal, to optimize repeater performance for near-end crosstalk produced by other systems operating within the same cable bundle. The preamplifier output signals which are balanced and of opposite phase, are applied to the clock extraction and pulse regenerator circuits. Here they are rectified and then applied to a high Q resonant circuit which extracts the 1.544/2.048 Mbps frequency component from the received signal. This signal is then sliced and fed to an adjustable phase shift circuit. A second slicer is used to control the time at which the output signals from the preamplifier are sampled by the pulse regenerator circuits. The phase shifted clock signal is made available as an output from the circuit for interface applications. The clock phase adjustment is performed with a single pin using an external resistor. Adjustment of the position of the clock sampling edge by the phase shift circuit allows performance of the pulse regenerator to be optimized. The pulse regenerator performs the sampling and data slicing to regenerate the appropriate output pulse. These pulses are applied to an external output transformer to create the bipolar signal that drives the next section of twisted pair. Rev. 1.02 6 XR-T56L22 Typical ICC Vs. VCC Variation at T=25C (Clock, Data Outputs + ALBO all Operating) (VIN=6V p-p (@2.04MBPS) 7.8 7.6 7.4 7.2 I CC in (mA) 7.0 6.8 6.6 6.4 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 VCC in Volts Figure 2. Supply Current Variation with VCC (Regulator Inhibited) Max Clock Drive Current = 100mA @ Albo Thresholds Clk Drive ( m A) 1.8 1.6 1.4 1.2 1.0 .8 .6 .4 .2 120 110 100 90 80 70 60 50% CLK Drive Max 50 40 30 20 10 0 .2 .4 .6 .8 1.0 1.2 1.4 1.6 1.8 VALBOTHLD = 1.44 CLK VCLKTHLD = 1.02v VPREAMP OUT (V) CLK THLD(+) ALBO THLD(+) Figure 3. Clock Drive Current Against Preamp Output Voltage Rev. 1.02 7 XR-T56L22 50 40 30 20 0 -10 -20 -30 -40 10 Differential Gain Phase Phase in Degrees Frequency In Hertz 106 107 108 60 0 -45 -90 -135 Gain A V IN DS -180 104 105 Figure 5. Preamp Gain/Phase Characteristics Preamp Output (Approx. 1.5 pK to pK) Oscillator Input Pin 16 Clock Output Pin 12 Data Pos. Pin 18 Data Neg. Pin 1 Figure 4. Typical T56L22 Waveforms Rev. 1.02 8 XR-T56L22 + C11 15F IM R1 3.9K R2 100 R3 51 C3 1F R5 100 C4 1F VCC R8 130 D+ C2 8.22UF C1 8.22UF 1 18 C18 2 17 3 16 4 15 R13 1F 51 C7 8.1F R11 1.8K C8 8.22F C9 8.1F R7 680 R4 8.2K R6 7.5K 5 14 6 13 VCC C5 8.22F + 7 12 R18 8 11 C6 47F 1K R9 138 D- CLK 9 10 Figure 6. AC Parameter Test Circuit Rev. 1.02 9 XR-T56L22 Rev. 1.02 10 Figure 8. XR-T56L22 E1 Evaluation Circuit Rev. 1.02 11 XR-T56L22 Figure 9. XR-T56L22 T1 Evaluation Circuit XR-T56L22 18 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 18 1 D A L 10 9 E1 E A2 Seating Plane A1 B e B1 eA eB C INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.845 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.925 0.325 0.280 MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 21.46 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 23.50 8.26 7.11 0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15 2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15 Note: The control dimension is the inch column Rev. 1.02 12 XR-T56L22 18 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP) Rev. 1.00 18 10 1 9 E D Base Plane Seating Plane L e B B1 c A1 A E1 INCHES SYMBOL A A1 B B1 c D E1 E e L MIN 0.100 0.015 0.014 0.045 0.008 0.860 0.250 MAX 0.200 0.070 0.026 0.065 0.018 0.960 0.310 MILLIMETERS MIN 2.54 0.38 0.36 1.14 0.20 21.84 6.35 MAX 5.08 1.78 0.66 1.65 0.46 24.38 7.87 0.300 BSC 0.100 BSC 0.125 0.200 7.62 BSC 2.54 BSC 3.18 5.08 15 0 15 0 Note: The control dimension is the inch column Rev. 1.02 13 XR-T56L22 18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) Rev. 1.00 D 18 10 E 1 9 H C Seating Plane e B A1 L A INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.447 0.291 MAX 0.104 0.012 0.020 0.013 0.463 0.299 MILLIMETERS MIN 2.35 0.10 0.33 0.23 11.35 7.40 MAX 2.65 0.30 0.51 0.32 11.75 7.60 0.050 BSC 0.394 0.016 0 0.419 0.050 8 1.27 BSC 10.00 0.40 0 10.65 1.27 8 Note: The control dimension is the millimeter column Rev. 1.02 14 XR-T56L22 Notes Rev. 1.02 15 XR-T56L22 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1997 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.02 16 |
Price & Availability of XR-T56L22AN
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |